Viterbi bit detection method and device

ABSTRACT

A Viterbi bit detection method for detecting the bit values of bits of a channel data stream stored on a record carrier along an N-dimensional channel tube, N being at least two, of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along at least a second of N−1 other directions, the first direction together with the N−1 other directions constituting an N-dimensional lattice of bit positions, includes application of a row-based one-dimensional Viterbi bit detection method independent for each of the bit rows of said channel tube. To achieve a reliable bit detection, a number of independent one-dimensional row-based Viterbi bit detectors, also known as sequence detectors, is used, one for each bit row in the channel tube: the interference between successive neighboring bit rows is taken into account via the computation of the branch metrics (for the considered bit row), in which local bit decisions on the primary neighboring bits in the neighboring rows are used. As local bit detectors going beyond the performance of a threshold detector, the use of a HD-2 or HD-3-like hard-decision bit detector is proposed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a row-based Viterbi bit detectionmethod for detecting the bit values of bits of a channel data streamstored on a record carrier. Further, the present invention relates to acorresponding row-based Viterbi bit detector, a method of reproductionof a user data stream, a corresponding reproduction device and acomputer program for implementing said methods. In particular, thepresent invention relates to a row-based Viterbi bit detection methodfor information written in a two-dimensional way on a record carrier,such as an optical disc or a memory card. The present invention couldalso be regarded as relating to Partial Response Maximum-Likelihood(PRML) bit detection, i.e., the invention also relates to a PRLM bitdetection method and device.

2. Description of the Related Art

European Patent Application No. 01203878.2 discloses a method and systemfor multi-dimensionally coding and/or decoding an information to/from alattice structure representing channel bit positions of said codedinformation in at least two dimensions. Encoding and/or decoding isperformed by using a quasi close-packed lattice structure. For the caseof three-dimensional encoding and/or decoding, preferably a (quasi)hexagonally close packed (hcp) lattice structure is to be used. Anotherpossibility in three dimensions is the use of a (quasi) face-centeredcubic (fcc) lattice structure. For the case of two-dimensional encodingand/or decoding, preferably, a quasi-hexagonal lattice structure is tobe used. Another possibility in two dimensions could be the use of aquasi square lattice structure. For the sake of a more simple and cleardescription of the object of the present invention, special attention isgiven to the two-dimensional case. The higher-dimensional cases can bederived as more or less straightforward extensions of thetwo-dimensional case. The special situation of the one-dimensional casewhich comprises only a single row of bits, boils down to the veryclassical case of PRML bit detection as is well known in the state ofthe art for one-dimensional modulation and coding, as, for instance,described in Chapter 7 “Viterbi Detection” by Jan Bergmans, “DigitalBaseband Transmission and Recording”, Kluwer Academic Publishers, 1996.

In one-dimensional recording on optical discs, the channel bits of thechannel data stream are recorded along a spiral track, the spiral beingone bit wide. For two-dimensional recording, the channel bits of achannel data stream can also be recorded along a spiral, albeit a broadspiral, that consists of a number of bit rows which are aligned withrespect to each other in the radial direction, that is, in the directionorthogonal to the spiral direction. The additional alignment of bit rowscan also be obtained in another direction not strictly orthogonal to thespiral direction, but in a direction making a certain non-zero anglewith the spiral direction.

A PRML bit detection apparatus for deriving a bit sequence from an inputinformation signal is disclosed in WO 00/18016, corresponding to U.S.Pat. No. 6,580,766. The apparatus comprises input means for receivingthe input information signal, sampling means for sampling the inputinformation signal at sampling instants so as to obtain samples of theinput information signal at said sampling instants, conversion means forconverting an array of said samples into an array of bits of a first ora second binary value, detection means for repeatedly detecting a statefor subsequent sequences of n subsequent bits of said array of bits,said subsequent sequences being obtained by shifting a time window of nsubsequent bits each time over one bit in time, means for establishingthe best path through the states, and deriving means for deriving asequence of bits in accordance with the best path through said states.In that apparatus, n is larger than 3, and sequences of n subsequentbits having n−1 directly successive bits of the same binary value areallocated to the same state. In a specific embodiment, n is an oddnumber larger than 4. In that specific embodiment, sequences of nsubsequent bits having n−2 directly successive bits of the same binaryvalue as the central n−2 bits in such n-bit sequence, are allocated tothe same state. This results in a PRML detection apparatus with reducedcomplexity.

A full-fledged PRML bit detector for 2D bit-arrays would require atrellis which is designed for the complete width of the broad spiral,with the drawback of an enormous state-complexity that leads to acompletely impractical algorithm, since it cannot by far be implementedeven in the fastest hardware of the coming decennia.

A 2D PRML bit detector is disclosed in “Study of Recording Methods forAdvanced Optical Disks”, S. Taira, T. Hoshizawa, T. Kato, Y. Katayama,T. Nishiya, T. Maeda, Technical Report of IEICE, 2002–03, pp. 57–64.Therein, an optical storage system with 2D modulation on a squarelattice, with d=1 RLL constraints both in horizontal and verticaldirections is described. For this system, a receiver, consisting of a2D-equalizer and a 2D-Viterbi detector or a 2D-PRML detector, isdisclosed in “Two-Dimensional Partial-Response Equalization andDetection Method with Multi-Track”, T. Kato, S. Taira, Y. Katayama, T.Nishiya, T. Maeda, Technical Report of IEICE, 2002–03, pp. 65–70. The 2DPRML detector is based on three successive bit rows, but the typicaladd-compare-select operation (ACS) of the Viterbi-algorithm uses theHF-samples of the central bit row only; the other two bit rows are usedin order to determine, in a joint way, the reference level from whichthe received HF-signal should be subtracted in order to derive thebranch metrics for the branches (or transitions) in the trellis diagramof the Viterbi detector. In this way, at its output, theViterbi-detector yields bit-decisions for the central bit row only. Inthis sense, for successive rows, the PRML detectors operate alreadyindependently, and the state-complexity for the complete set of bit rowshas been reduced down to the complexity that is to be associated with 3rows only. Within a strip of 3 rows, the known bit detector performs akind of 2D-PRML, but with a 1D-output (for the single row being themid-row of the 3-row strip). It should be noted that the channel stripsare processed independently, but that the state-complexity of theViterbi-detector is still quite high.

Assuming the practical case of a 3-taps response in the tangentialdirection, as disclosed in the above mentioned documents. For the squarelattice, but also when applying this algorithm for a hexagonal lattice,assuming no modulation coding for both lattices, states characterized by6 bits each would be obtained, yielding a number of 2⁶=64 states; eachstate would then have 2³=8 possible predecessors. On the square lattice,assuming the runlength modulation coding of the above references with 2Dd=1 constraint, the number of states is only a bit smaller than 64,since some of the states are forbidden just because of the use of therunlength constraints along vertical and horizontal directions.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a Viterbi bitdetection method that provides a high recording density, in particular,such that the traditional “eye” of the eye pattern may even be closed.The “eye height” in the traditional eye-pattern corresponds with thesystematic minimum difference in signal levels for the case that a bithas a value “0” and the case that a bit has a value “1”. An “open eye”means that (on average, or without any noise) the signal levels for bit“0” and bit “1” can be clearly discriminated: in such case, a thresholddetection procedure with an appropriately set slicer level could beused. The case of a “closed eye” corresponds to the situation where someof the signal levels cannot unambiguously be allocated to bit “0” or bit“1”, even in the absence of noise. There is, in the latter case, a rangeof signal levels, called the erasure zone, where the signal levels forbit “0” and bit “1” overlap.

It is a further object of the present invention to achieve a low biterror rate, which is particularly less than 10⁻² to 10⁻¹ as would beachieved for the case of a “closed eye” by application of astraightforward threshold detection prior to ECC decoding. Preferably,the symbol or byte error rate (BER) for “random” errors (as opposite toso-called “burst errors”) in the case of a byte-oriented ECC, like thepicket-ECC as used in BD (formerly known as DVR), shall not be largerthan 2×10⁻³; for an uncoded channel bit stream this corresponds to anupper bound on the allowable channel-bit error rate (bER) of 2.5×10⁻⁴.

Still further, a further reduction of the state-complexity of theindependent Viterbi-detectors shall be achieved.

These objects are achieved according to the present invention by aViterbi bit detection method, according to which the channel data streamis stored on a record carrier along an N-dimensional channel tube, Nbeing at least two, of at least two bit rows one-dimensionally evolvingalong a first direction and being aligned with each other along at leasta second of N−1 other directions, said first direction together withsaid N−1 other directions constituting an N-dimensional lattice of bitpositions, comprising application of a row-based one-dimensional Viterbibit detection method independent for each of the bit rows of saidchannel tube, wherein:

calculation of the branch metrics for all possible state transitions ina Viterbi trellis of a one-dimensional row-based Viterbi detector, saidtransitions representing a number of subsequent bits in said bit row,said bits being the central-row bits of a cluster of the N-dimensionallattice of bits, is based on the difference of the received HF signalvalue with respect to a reference level, wherein said reference leveldepends on all bits of said cluster, said cluster comprising in additionto the central-row bits a number of primary neighboring bits in each ofa number of neighboring bit rows on each side along said N−1 otherdirections of said central bit row along which the one-dimensionalViterbi bit detection method is applied, and wherein preliminary bitdecisions for the primary neighboring bits in the neighboring bit rowsare used for determining the reference level to be used for calculatingsaid branch metrics, and

selection of the bit value for the central bit of said cluster of theN-dimensional lattice of bits, corresponding with said received HFsignal value, is based on the calculated branch metrics.

These objects are further achieved by a row-based Viterbi bit detectorcomprising Viterbi bit detection units including means for calculationof the branch metrics and means for selection of a bit value. Theinvention relates further to a method of reproduction of a user datastream, which is error correction code encoded and modulation codeencoded into a channel data stream and stored on a record carrier,comprising a Viterbi bit detection method as described above fordetecting the bit values of bits of the channel data stream and amodulation code decoding method and an error correction code decodingmethod. Still further, the present invention relates to a reproductiondevice and a computer program.

The present invention is based on the idea to achieve reliable bitdetection by using a number of independent 1D Viterbisequence-detectors, one for each bit row in the channel tube: theinterference between successive neighboring bit rows is taken intoaccount via the computation of the branch metrics for the considered bitrow, in which preliminary bit decisions on the primary neighboring bitsare used that may require local bit decisions on the secondaryneighboring bits in the neighboring bit rows, said secondary neighboringbits being the neighboring bits of said primary neighboring bits notbeing part of the central bit row being considered for the 1D Viterbidetection.

Regarding the general layout and function of a PRML bit detectionapparatus, reference is made to the above-mentioned WO 00/18016 wherealso several terms are explained. This description and explanation isherein incorporated by reference.

In preferred embodiments for determining the preliminary bit decisionson the primary neighboring bits, a slicer level can be used in athreshold detection. Further, specific bit values of the bits in thecentral row can be used in accordance with each of the specific branchesto be considered in the Viterbi trellis. Said threshold detection isbased on the detected HF signal value for a particular bit withoutconsideration of the HF-signal samples at the neighboring bit-locations.

According to a preferred embodiment, a predetermined criterion isevaluated for determining the preliminary bit decisions, this criterionbeing determined by the sum over all the primary neighboring bits, saidsum comprising terms related to a subcriterion that is based on thedifferences of the HF signal value and a reference HF signal valuecorresponding to the bit cluster of each single primary neighboring bit,the evaluation being done for all possible bit units obtained for allpossible values of said primary neighboring bits, and wherein the bitunit with the lowest value of said predetermined evaluation criterion isselected. Preferred subcriteria relate to the squared value or theabsolute value of the difference of the HF signal value and a referenceHF signal value corresponding to the bit cluster of each single primaryneighboring bit.

In addition to the primary neighboring bits, preliminary bit decisionson secondary neighboring bits can be used for determining thepreliminary bit decisions on the primary neighboring bits. Thosepreliminary bit decisions on said secondary neighboring bits can beobtained, for instance, by threshold detection.

There are different ways to calculate the branch metrics. The Viterbialgorithm in a PRML bit detector searches for the “best” path, that is,the path with the minimum path cost. The path cost is sometimes called“path metric”. A path can be seen as a succession of transitions. Atransition from one state to another state is called a branch. Eachtransition (or branch) has associated with it a certain branch metric(or branch cost). The path metric for a given path is the sum of thecosts of the individual branches of the path, that is, the path metricis a sum of a selection of branch metrics.

Generally, the present invention is applicable to a multi-dimensionalcode, where the channel words of the channel data stream may evolve inmore than one direction as is the case for a card-based system, i.e.,where the channel data stream is stored on a record carrier along amulti-dimensional channel tube with dimension at least two. Therein, thefirst direction along which the bit rows evolve is preferably common toall bit rows of the channel tube. The first direction constitutes,together with the N−1 other directions, along which the bit rows arealigned with each other, an N-dimensional space and an N-dimensionallattice of bit positions. The channel tube comprises at least two bitrows of channel bits evolving along said first direction, and thecollection of all said channel tubes fill the whole N-dimensional space.

However, it is preferred to apply the invention to a channel data streamwhich comprises a one-dimensionally evolving bit sequence, or whichcomprises a channel strip of at least two bit rows one-dimensionallyevolving along a first direction and aligned with each other along asecond direction, preferably oblique or even orthogonal to said firstdirection, said two directions constituting a two-dimensional lattice ofbit positions. Preferred embodiments of such a lattice are a 2D latticeof a square or a hexagonal type.

In a hexagonal lattice, hexagonal clusters may be formed of a set of 7bits in total, comprising three bits in a central bit row and twoprimary neighboring bits in each of the two neighboring bit rows.Further secondary neighboring bits can be located in the neighboring bitrows of the central bit row considered. Preferred embodiments of theinvention use hexagonal clusters.

An advantageous embodiment for calculation of the branch metrics uses anexpectation value. The method can also be applied in thethree-dimensional case where the bits are location on bit positions of athree-dimensional lattice.

The bit detection method according to the invention can also include aniterative use of the row-based one-dimensional Viterbi bit detectionmethod: the output of the 1D-Viterbi detectors for a given 1D part ofthe set of bit rows can be used for the required primary bit decisionsin the neighboring rows during a second run of the method for the same1D part (same bits along the 1D row) of the set of rows. The purpose isto use the output of the first set of 1D-Viterbi detectors for all bitrows as a better bit decision for the primary bit decisions required ina possible second set of Viterbi detectors for all bit rows.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention shall now be explained with reference to the drawings, inwhich:

FIG. 1 shows a block diagram of a general layout of a coding system;

FIG. 2 shows a schematic diagram indicating a strip-basedtwo-dimensional coding scheme;

FIG. 3 shows a schematic signal-pattern for a two-dimensional code onhexagonal lattices;

FIG. 4 shows a row-based partitioning of the 2D target response on thehexagonal bit cluster;

FIG. 5 shows a Finite-State-Machine for an 1D-PRML with 3-tap PRMLtarget;

FIG. 6 shows a hexagonal bit-cluster with enumeration convention used inthis application;

FIG. 7 illustrates the invention in case two primary neighboring bitsare used;

FIG. 8 illustrates the invention in case three primary neighboring bitsare used;

FIG. 9 shows a trellis for 1D-PRML bit detection;

FIG. 10 shows a repeated trellis for 1D-PRML bit detection;

FIG. 11 illustrates a particular example using the trellis shown in FIG.9;

FIG. 12 illustrates the determination of the path cost according to thepresent invention;

FIG. 13 shows a block diagram of a bit detector in case two primaryneighboring bits are used in each primary neighboring bit row;

FIG. 14 shows the HF reference signal levels used in the bit detectorshown in FIG. 13;

FIG. 15 shows a single bit detection unit of a bit detector shown inFIG. 13;

FIG. 16 shows a Fermi-Dirac like S-curve for deriving soft-decisioninformation from a HF-signal of a bit;

FIG. 17 shows reference levels derived from the signal pattern; and

FIG. 18 shows the bit-error-rate as a function of SNR (defined relativeto the full-reflection signal level) for a typical density.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows typical coding and signal processing elements of a datastorage system. The cycle of user data from input DI to output DO caninclude interleaving 10, error-correction-code (ECC) and modulationencoding 20, 30, signal preprocessing 40, data storage on the recordingmedium 50, signal post-processing 60, binary detection 70, and decoding80, 90 of the modulation code, and of the interleaved ECC. The ECCencoder 20 adds redundancy to the data in order to provide protectionagainst errors from various noise sources. The ECC-encoded data are thenpassed on to a modulation encoder 30 which adapts the data to thechannel, i.e., it manipulates the data into a form less likely to becorrupted by channel errors and more easily detected at the channeloutput. The modulated data are then input to a recording device, e.g., aspatial light modulator or the like, and stored in the recording medium50. On the retrieving side, the reading device (e.g., photo-detectordevice or charge-coupled device (CCD)) returns pseudo-analog data valueswhich must be transformed back into digital data (one bit per pixel forbinary modulation schemes). The first step in this process is apost-processing step 60, called equalization, which attempts to undodistortions created in the recording process, still in the pseudo-analogdomain. Then, the array of pseudo-analog values is converted to an arrayof binary digital data via a bit detector 70. The array of digital datais then passed first to the modulation decoder 80, which performs theinverse operation to modulation encoding, and then to an ECC decoder 90.

In the above-mentioned European Patent Application No. EP 01203878.2,the 2D constrained coding on hexagonal lattices in terms ofnearest-neighbor clusters of channel bits is described. Therein, it hasbeen focused mainly on the constraints with their advantages in terms ofmore robust transmission over the channel, but not on the actualconstruction of such 2D codes. The latter topic is addressed in EuropeanPatent Application No. 02076665.5 (PHNL 020368), i.e., theimplementation and construction of such a 2D code is described therein.By way of example, a certain 2D hexagonal code shall be illustrated inthe following. However, it should be noted that the general idea of theinvention and all measures can be applied generally to any 2D code, inparticular, any 2D hexagonal or square lattice code. Finally, thegeneral idea can also be applied to multi-dimensional codes, possiblywith isotropic constraints, characterized by a one-dimensional evolutionof the code.

As mentioned, in the following, a 2D hexagonal code shall be considered.The bits on the 2D hexagonal lattice can be identified in terms of bitclusters. A hexagonal cluster consists of a bit at a central latticesite, surrounded by six nearest neighbors at the neighboring latticesites. The code evolves along a one-dimensional direction. A 2D stripconsists of a number of 1D rows, stacked upon each other in a seconddirection orthogonal to the first direction. The principle ofstrip-based 2D coding is shown in FIG. 2. Between the strips or betweengroups of successive strips, a guard band of, for instance, one row maybe located.

The signal-levels for 2D recording on hexagonal lattices are identifiedby a plot of amplitude values for the complete set of all hexagonalclusters possible. Use is further made of the isotropic assumption, thatis, the channel impulse response is assumed to be circularly symmetric.This implies that, in order to characterize a 7-bit cluster, it onlymatters to identify the central bit, and the number of “1”-bits (or“0”-bits) among the nearest-neighbor bits (0, 1, . . . , 6 out of the 6neighbors can be a “1”-bit). A “0”-bit is a land-bit in our notation. Atypical “Signal-Pattern” is shown in FIG. 3. Assuming a broad-spiralconsisting of 11 parallel bit rows, with a guard band of 1 (empty) bitrow between successive broad spirals, the situation of FIG. 3corresponds to a density increase with a factor of 1.7 compared totraditional 1D optical recording (as used in e.g., in the Blu-ray Disc(BD) format (using a blue laser diode)).

According to the present invention, the broad spiral (or meta-spiral)consists of a number of bit rows. It is proposed to apply a row-based1D-PRML, in which the Viterbi-trellis relates only to the bits in theindividual bit row itself. For a 3-tap target response in the directionalong the bit row, states are obtained that are each defined by twobits. FIG. 4 shows the 2D target response on the cluster of bits of thehexagonal lattice. The corresponding Finite-State Machine (FSM) is shownin FIG. 5. The FSM reveals the syntax when going from one state “i”(with bits (b₀ ^(i) b₁ ^(i))) towards another state “j” (with bits (b₀^(j) b₁ ^(j))). Such a transition between states “i” and “j” is onlyallowed on the condition that b₁ ^(i)=b₀ ^(j), i.e., the second bit ofthe first state and the first bit of the second state must be identical.It should be noted that a transition from one state “i” to another state“j” completely characterizes the three bits of the 7-bits cluster at thecentral bit row by (b₀ ^(i) b₁ ^(i) b₁ ^(j)). No further restrictionsare present on the possible transitions, because in the practicaldescription made here, there is no 1D RLL constraint assumed for thecase of our 2D hexagonal-lattice modulation.

Next, the computation of branch metrics shall be explained. FIG. 6 showsthe enumeration of the 7 bits of an hexagonal cluster: x₀, x₁, x₂, x₃,x₄, x₅, and x₆. The branch metric for the transition from state “i” tostate “j” is denoted by β_(ij). It is preferably given by:β_(ij)=(HF ₀ −R.L.[x ₀ =b ₁ ^(i) ; x ₁ =b ₁ ^(j) ; x ₂ ; x ₃ ; x ₄ =b ₀^(i) ; x ₅ ; x ₆])²where HF₀ denotes the sample value of the (possibly equalized) receivedsignal at the (central) bit x₀. R.L. denotes the reference amplitudelevel, which depends on all the bit-values of the 7-bit cluster. For agiven transition (“i” to “j”), the values of the bits x₀, x₁ and x₄ inthe central bit row are already fixed. The other bits that still need tobe determined, occur in two pairs of bits, denoted by x₂, X₃ and x₅, x₆.These pairs correspond with nearest neighbor bits of the central bit x0,where each of these pairs is located either in the upper neighboring bitrow, or in the lower nieghboring bit row. The bit values in these twobit-pairs are required in order to be able to uniquely identify thereference level R.L. to be used in the branch metric for the transitionsin the 1D-PRML detector for the considered bit row. These bits will befurther referred to as the primary neighboring bits. Therefore, thesebit decisions on the primary neighboring bits can be seen as preliminarybit decisions, needed to assist the evaluation of the branch metricsrequired for the bit decisions of the bit in the considered (central)bit row. One aspect of the present invention relates to the decisionsthat are to be made on those two bit-pairs of primary neighboring bits.The quality of these (temporarily needed) preliminary bit decisions thatare (only) required for the computation of branch metrics, have animpact on the quality of the ultimate bit decisions of the bits in thecentral row on which the 1D-PRML is applied. The preliminary bitdecisions on the primary neighboring bits are thus never used as realoutput bits for the neighboring bit rows.

A rather straightforward approach is to use threshold detection for theprimary neighboring bits denoted by x₂ and x₃ and x₅ and x₆. However,threshold detection is highly unreliable due to the large overlap insignal levels in the signal pattern shown in FIG. 3. In the performanceanalysis, it turns out that not much performance gain is obtained fromthe use of 1D-PRML with threshold detection for the primary neighboringbits compared to threshold detection applied as the bit detector on thewhole meta-spiral. The quality of the primary neighboring bit decisionsis obviously not good enough.

More reliable bit decisions at the primary neighboring bits can beobtained through the use of the hard-decision bit detectors onnearest-neighbor bits in neighboring bit rows.

FIG. 7 illustrates the use of a HD-2 (HD=hard-decision) bit detectorwhich uses preliminary bit decisions on a doublet of two primaryneighboring bits in each of the upper and lower neighboring bit row ofthe central bit row. As explained above, the bit values of the bits inthe central bit row are fixed for a given branch in the trellis. Thebit-values of the primary neighboring bits in the neighboring bit rowsare determined as follows, wherein the bit-pairs (also referred to asbit units) denoted by x₂ and x₃, and x₅ and x₆ are treated independentof each other: a criterion, preferably the sum of two terms, each termbeing a square of a difference of the actual received HF sample at onebit of the bit pair with the corresponding reference level for thatprimary neighboring bit in the bit pair, is evaluated for all possibletwo-bit combinations of the bits in the bit pair. The bit-pair which hasthe lowest value for the criterion is selected. This yields thepreliminary bit values to be used in the reference level for the branchmetric at the bit x₀ in the central row. But also for the primaryneighboring bit values, reference levels need to be specified for thecriterion of the HD-2 detector. Therefore, the bit values of allnearest-neighbor bits for each bit of the two bit pairs of primaryneighboring bits are needed as well. Some of these neighbors are fixedby the branch considered, others are part of the HD-2 selectionprocedure; all other remaining nearest-neighbor bits for each primaryneighboring bit of the two bit-pairs are referred to as secondaryneighboring bits, which may preferably be obtained by thresholddetection (TD).

FIG. 8 illustrates the use of a HD-3 bit detector which uses preliminarybit decisions on triplets of three primary neighboring bits in the twoupper and the two lower neighboring bit rows of the central bit row. Theprocedure is quite similar to the one explained above for the HD-2 bitdetector. Preliminary bit decisions are required at the primaryneighboring bits of the two bit pairs denoted by x₂ and x₃, and x₅ andx₆. Each bit pair is again processed independently. To each bit pair isadded a third bit in the second neighboring bit row of the central bitrow so that a bit-triplet (also referred to as bit unit) is formed.There are 8 possible bit-triplets. As above, a criterion is evaluatedfor each of these 8 possibilities, and the one with the lowest value isselected. The criterion used for the HD-3 bit detector is a sum of threeterms, one for each bit in the triplet. Each term corresponds to one bitin the triplet, and preferably is the squared value of the differencebetween the measured HF signal at that bit and the correspondingreference level. The latter is determined by using bit values of thenearest-neighbor bits of the bits in the triplets; some of these nearestneighbor bits are fixed by the branch considered, others are part of theHD-3 selection procedure, and yet other bits, i.e., the 6 bitssurrounding the bit-triplet in the neighboring bit rows of the centralbit row, which bits are further referred to as secondary neighboringbits, may preferably be determined by threshold detection (TD). From thechosen bit-triplet, only the bits of the bit pairs x₂ and x₃ for thebottom bit-triplet, and x₅ and x₆ for the top bit-triplet are needed inorder to choose the reference level that has to be used in thecomputation of the branch metric for the 1D-PRML at the bit x0 in theconsidered bit row (assuming that the intersymbol-interference of whichthe bit detector can take care of resides within a hexagonal clustercomprising not more than 7 bits). However, inclusion of the extra thirdbit in each of both 3-bit bit units may largely improve the quality ofthe preliminary bit decisions on the primary neighboring bit pairs x₂and x₃ for the bottom bit-triplet, and X₅ and x₆ for the topbit-triplet.

The trellis for 1D-PRML bit detection with 3-taps impulse-response inthe tangential direction is illustrated in FIG. 9. As can be seen, eachstate has exactly two predecessor states.

These two predecessor states are the states that have, as a last bit,the first bit of the current (considered) state. For instance,transitions from state “01” are only allowed for the states “10” and“11” as next state. These transitions yield the 3-bit sequences “010”and “011”, respectively.

FIG. 10 shows the repeated trellis for 1D-PRML bit detection with 3-tapsimpulse-response in the tangential direction.

All paths through the trellis realize all possible bit sequences. TheViterbi algorithm (for maximum-likelihood sequence detection) searchesfor the “best” path, that is, the path with the minimum path cost. Thepath cost is sometimes called “path metric”. A path can be seen as asuccession of transitions. A transition from one state to another state(from moment k towards moment k+1) is also called a branch. Eachtransition (or branch) has associated with it a certain branch metric(or branch cost). The path metric for a given path is the sum of thecosts of the individual branches of the path, that is, the path metricis a sum of branch metrics.

For the above case (with 2-bits states “00”, “01”, “10” and “11”), abranch metric for a transition between states s0 and s1, from moment (ortime) k−1 to moment k, is the squared value for the L2-norm (or absolutevalue for the L1-norm) of the difference between the measured HF-sampleat time k (denoted by HFk) and the reference level R.L. that isassociated with the transition from state s0 to state s1. The referencelevel is a kind of ideal (noise-free) signal level for the transitionthat is considered.

The reference level here also depends on the bit values of theneighboring bit rows, because of the strong 2D inter-symbol-interference(ISI). In standard 1D-storage, the neighboring bit rows are always faraway so that this problem is not present there.

The applied Viterbi algorithm shall now be explained with reference toFIG. 11. Finding the best path via a brute force (exhaustive) search isnot favorable because of the computational burden. Viterbi hasintroduced the procedure of “dynamic programming” with a complexity thatis linearly growing with the length of the bit-sequence to bedetermined. In the following, it shall be assumed that the best path attime k that arrives in state “01” shall be found. It is further assumedthat the following two aspects for each of the states have previouslybeen evaluated at time k−1:

(a) for each state, the path metric for the best path, i.e., the pathwith minimum cost, that arrives in that state, is known;

(b) for each state, the predecessor state at the previous time is known:the predecessor state is the state that lies on the best path at theprevious time moment.

Then, the best path at moment k that arrives in “01” can be found bylooking at the two possible predecessor states of state “01”: one pathstarts in state “00” with a path metric p_(00,k−1) and needs a branch“00”->“01” to arrive in state “01”, with a branch metric given byb_(00->01,k). The second path starts in state “10” with a path metricp_(10,k−1) and needs a branch “10”->“01” to arrive in state “01”, with abranch metric given by b_(10->01,k). The best path is the path thatrealizes the minimum cost:minimum of p _(00,k−1) +b _(00->01,k) and p _(10,k−1) +b _(10->01,k).If the latter is the best path, then the predecessor state of state “01”is “10”, in the other case, the predecessor state of state “01” is “00”.This procedure is known as Add-Compare-Select (ACS): the branch metricis added to the previous path metric to obtain a candidate for thecurrent path metric; the two candidate path metrics are compared, andthe path with the lowest metric is selected.

This procedure is repeated for all states (at each time moment). As aresult, a collection of path metric and predecessor state for each stateand each time moment is obtained. The actual bit detection is thenperformed by a so-called back-tracking operation: one starts from a beststate at moment k, and goes back to its predecessor state at time k−1,and to the predecessor state of that state at moment k−2, and so on. Theback-tracking is done for a certain depth K (known as back-trackingdepth); the bit value at moment k−K is (for instance) the bit-value ofthe first bit in the resulting state obtained at the end of theback-tracking operation. States “00” and “01” lead to bit “0”; states“10” and “11” lead to bit “1”.

There are four states, denoted by “00”, “01”, “10” and “11”. For each ofthese states, the best predecessor of that state and the path costs upto the given state for the path with the lowest cost going to that stateare evaluated, as illustrated in FIG. 12. For state “00”, for instance,possible predecessor states are the states “00” and “10”, leading to thebits “000” (from state “00” towards state “00”) and “100” (from state“10” towards state “00”) for the triplet of bits denoted by (b₄, b₀,b₁), as denoted by the upper and lower line related to state “00”. Theseseparate transitions towards state “00” are called branches of thetrellis. The bit b₀ is the central bit of the triplet. For a givenstate, thus two possible branches are there. For each of the branches,the most likely candidates for the bits b₂ and b₃ in the lower rowrelative to the considered row, and for the bits b₅ and b₆ in the upperrow relative to the considered row are determined.

According to the embodiment shown in FIG. 12, this is done by using anHD-2 detector for each of the two bit-pairs (b₂ and b₃) and (b₅ and b₆):the respective HD-2 detectors are denoted by “HD-2 Upp” and “HD-2 Low”in FIG. 12. The resulting four bits (b₂ and b₃, b₅ and b₆) together withthe bits of the bit-triplet (b₄, b₀, b₁) define the 7 bits of thehexagonal cluster: these 7 bits uniquely define an index for thespecific reference level in the memory of Reference Levels, the latterbeing denoted by HF Ref.Lev.Mem. The reference levels for each of thetwo branches (for each of the four states) is compared with the actuallymeasured HF signal for bit b₀, denoted by HF. Such comparison can bedone by a squared value in case of the L2-norm (or absolute value incase of the L1-norm) of the difference of the received signal and thereference level: such difference value yields the actual branch metricfor each of the two transitions in the trellis. A standardAdd-Compare-Select (ACS) unit that uses the current branch metrics andthe path metrics up to the two possible preceding states, i.e., “00” and“10” in the case of state “00”, further determines the best predecessorof the current state, denoted as pre₀₀, and the path cost for thecheapest path up to the currently considered state “00”, denoted bypaco₀₀. This procedure is done for each of the four possible statesseparately and independently, since no information exchange is neededbetween the distinct procedures for each of the four states.

FIG. 13 shows the HD-2 bit detector HD-2 Upp for the determination ofthe upper-row bits (b₅ and b₆). The HD-2 Upp block has as input 8 bitvalues of the neighboring bits, three of which are set by the consideredbranch in the trellis for the central row, which is the row underconsideration; the other 5 bits are referred to as secondary neighboringbits, and are obtained as simply threshold-detected bits derived fromthe HF-samples at the corresponding bit-positions. The HD-2 Upp blockalso has two HF-samples as input for the bit-locations of bits b₅ andb₆.

The so-called “branch-bits” apply for the three bits of a giventransition in the trellis for the bit row under consideration.

A similar diagram (not shown) applies for the block HD-2 Low, yieldingbit decisions in the lower row for the bits denoted by b₂ and b₃. Thebits determined by the HD-2 Upp block are further used, together withthe similarly derived—by means of block HD-2 Low—lower bits b₂ and b₃ toderive reference levels from a reference level memory as shown in FIG.12.

Reference levels to be used in the core of HD-2 bit detector are shownin FIG. 14. The bit-numbering applied in FIGS. 14 and 15 should be notedwhich refers to the order of the bits in the bit pair. For the first bitin the bit pair, bit b₀, the reference levels are denoted with the firstsub-script underlined; for the second bit in the bit pair, bit b₁, thereference levels are denoted with the second sub-script underlined.

FIG. 15 shows the basic layout of the HD-2 bit detector block. Thisblock describes both the HD-2 Upp and the HD-2 Low blocks. Inputted are8 nearest neighboring bits on the hexagonal lattice and HF-samples ofthe two bits of the bit pair that needs to be updated. Outputted are thetwo updated bit values, i.e., the HD-2 detected bits. For each hexagonalcluster with one central bit and 6 neighboring bits, a reference signallevel is available from a memory, i.e., the HF Reference-Level Memory.The reference level to be taken from the memory is determined by the twobits of the bit pair, and by 5 out of the 8 neighboring bits of the bitpair. The 8 neighboring bits of the bit pair comprise 3 bits of thecentral bit row (determined by the actual branch considered), and 5secondary neighboring bits.

The received HF-signal for each bit of the two bits of the bit pair aresubtracted from the corresponding reference level; the absolute values(shown here; it may also be any other “norm” like the quadratic normusing the squared values instead) of these respective signal differencesare added together for each of the four possible two-bit configurationsfor the two bits of the bit pair. The bits that result from the HD-2 bitdetector are those that lead to the smallest value of the above set of 4parameters or samples of the selection criterion, one sample for eachpossible bit pair. This is denoted in FIG. 15 in short-hand notation byarg min: the arguments (bits b₀ and b₁ of the bit pair) for which thecriterion is at the minimum.

According to an alternative embodiment, soft-decision information aboutthe primary neighboring bits in the bit pairs (denoted by x₂ and x₃, andx₅ and x₆) is used. The branch metric for a given transition from state“i” to state “j” is then computed as an expectation value, which is theaverage taken over all possible bit-configurations in the two bit pairsof primary neighboring bits. Formally, this can be written as (with theindex k to the HFk signal referring to the sample at the k-th bit in thehexagonal cluster):

$\beta_{ij} = {\sum\limits_{b_{2} = 0}^{1}{\sum\limits_{b_{3} = 0}^{1}{\sum\limits_{b_{5} = 0}^{1}{\sum\limits_{b_{6} = 0}^{1}{{p\left( {{{x_{2} = b_{2}};{x_{3} = b_{3}};{x_{5} = b_{5}};{x_{6} = {{b_{6}❘x_{0}} = b_{1}^{i}}};{x_{1} = b_{1}^{j}};{x_{4} = b_{0}^{i}};{HF}_{2}},{HF}_{3},{HF}_{5},{HF}_{6}} \right)}\left( {{HF}_{0} - {R.L.\left\lbrack {{x_{0} = b_{1}^{i}};{x_{1} = b_{1}^{j}};{x_{2} = b_{2}};{x_{3} = b_{3}};{x_{4} = b_{0}^{i}};{x_{5} = b_{5}};{x_{6} = b_{6}}} \right\rbrack}} \right)^{2}}}}}}$

It should be noted that the bit values denoted by (b₀ ^(i), b₁ ^(i))refer to the two bits in state “i” of the 4-state Viterbi-trellis (shownin FIG. 9), and similarly for state “j”. The probability factor in theabove expression can be split into separate factors for each of the twoindependent bit pairs. For each bit pair, the factor can further besplit into factors relating to the individual bits, yielding:

p(x₂ = b₂; x₃ = b₃; x₅ = b₅; x₆ = b₆❘x₀ = b₁^(i); x₁ = b₁^(j); x₄ = b₀^(i); HF₂, HF₃, HF₅, HF₆) = p(x₂ = b₂❘all  6  nearest  neighbours  of  x₂; HF₂)  x  …  x  p(x₆ = b₆❘all  6  nearest  neighbours  of  x₆; HF₆) Just as in the HD-2 bit detector, reference can be made to FIG. 7, butnow primary neighboring bits of the bit pairs refer to bits withsoft-decision information. The nearest-neighbor bits of the bitpairs—those not part of the central bit row, nor from the HD-2 bit-unitare referred to as secondary neighboring bits—are determined bythreshold detection. For each bit of the bit pairs, all of itsnearest-neighbor bits are thus characterized. Soft-decision informationcan, for instance, be determined by a “Fermi-Dirac”-like S-curve asshown in FIG. 16 (given the configuration (“config”) of nearest-neighborbits, and the HF sample). Therein, Fermi-Dirac-like S-curves forderiving soft-decision information from the HF-signal of a bit atposition (k, 1) are shown. T₀ is the reference level when the centralbit (at (k, 1)) is a zero, T₁ applies for the case that the central bitis a one. The different curves relate to different noise variances. Thereference levels T₀ and T₁ are derived from the signal pattern as shownin FIG. 17 where an example is given when two nearest neighbor bits inthe hexagonal cluster are equal to “1”.

The performance for various detectors for the density of 1.4× thedensity of BD has been computed. A lattice parameter a=165 nm with apit-hole diameter equal to 120 nm (in order to avoid signal folding) hasbeen assumed. The channel is subjected to AWGN disturbance (additivewhite Gaussian noise). The detectors are:

threshold detection (TD);

HD-3 Hard-Decision Iterative Bit detector (HD-3);

TD-assisted 1D-PRML;

HD-2 assisted 1D-PRML;

HD-3-assisted 1D-PRML;

SD-1 Soft-Decision Iterative Bit detector (SD-1);

Soft-Decision-assisted 1D-PRML.

The results are shown in FIG. 18. Evaluation is done in terms of the(channel) bit-error-rate (bER), as a function of the SNR of the channel.It should be noted that the TD-assisted 1D-PRML has a high bER, that is,that version of the 1D-PRML detector offers only a marginal improvementin bER compared to the TD detector itself. The HD-3-assisted 1D-PRML, onthe other hand, is almost identical in performance to the soft-decisionbit detector SD-1, and slightly better than the hard-decision HD-3 bitdetector. The HD-3 assisted 1D-PRML is even better than the SD-assisted1D-PRML: this might be due to the fact that the soft-decisioninformation is obtained per bit only (and uses TD-decisions at some ofits neighbors), whereas, the HD-3 assisted 1D-PRML detector searches foroptimum joint (hard) bit-decisions in an area of 3-bits at each side ofthe considered track.

The present invention provides a solution to achieve reliable bitdetection by using a number of independent 1D-Viterbi bit detectors(also known as sequence detectors) is used, one for each bit row in thechannel tube: the interference between successive neighboring bit rowsis taken into account via the computation of the branch metrics (for theconsidered bit row), in which local bit decisions on the primaryneighboring bits in the neighboring rows are used. As local bitdetectors going beyond the performance of a threshold detector, the useof a HD-2 or HD-3-like hard-decision bit detector is proposed. Otherlocal bit detectors might also be used, insofar that they take accountof the specific bit values for the respective branches in the Viterbitrellis of the central row that is being processed with one-dimensionalrow-based Viterbi bit detector to condition the preliminary bitdetection for the primary neighboring bits in the neighboring rows ofthe considered bit row.

Further, it is proposed to use the output of a soft-decision bitdetector at the bits in the neighboring rows of the central row, inorder to compute the branch metrics. Practically, it is proposed to usesoft-decision information that can be directly generated from the signalpattern (with 2×7 signal levels, grouped as 7 pairs of levels). Ofcourse, other soft-decision bit detectors can be used for the samepurpose, like e.g., iterative soft-decision-detectors. Preferably, thetwo- and three-dimensional cases are advantageous where the bits arearranged on a two- or three-dimensional lattice.

1. A Viterbi bit detection method for detecting the bit values of bitsof a channel data stream stored on a record carrier along anN-dimensional channel tube, N being at least two, of at least two bitrows one-dimensionally evolving along a first direction and beingaligned with each other along at least a second of N−1 other directions,said first direction together with said N−1 other directionsconstituting an N-dimensional lattice of bit positions, said Viterbi bitdetection method comprising the steps of: applying a row-basedone-dimensional Viterbi bit detection method independent for each of thebit rows of said channel tube; calculating branch metrics for allpossible state transitions in a Viterbi trellis of a one-dimensionalrow-based Viterbi detector, said transitions representing a number ofsubsequent bits in said bit row, said bits being the central-row bits ofa cluster of the N-dimensional lattice of bits, said calculating beingbased on the difference of the received HF signal value with respect toa reference level, wherein said reference level depends on all bits ofsaid cluster, said cluster comprising, in addition to the central-rowbits, a number of primary neighboring bits in each of a number ofneighboring bit rows on each side along said N−1 other directions ofsaid central bit row along which the one-dimensional Viterbi bitdetection method is applied, and wherein preliminary bit decisions forthe primary neighboring bits in the neighboring bit rows are used fordetermining the reference level to be used for calculating said branchmetrics; and selecting the bit value for the central bit of said clusterof the N-dimensional lattice of bits, corresponding with said receivedHF signal value, based on the calculated branch metrics.
 2. The methodas claimed in claim 1, wherein the preliminary bit decisions on saidprimary neighboring bits in the neighboring bit rows are obtained bythreshold detection using a slicer level.
 3. The method as claimed inclaim 1, wherein the bit values of the central row constituting each ofsaid branches in the Viterbi trellis of the central row are used fordetermining the preliminary bit decisions on said primary neighboringbits in the neighboring bit rows.
 4. The method as claimed in claim 1,wherein the preliminary bit decisions on the primary neighboring bitsare obtained by evaluation of a predetermined criterion which isdetermined by the sum over all the primary neighboring bits, said sumcomprising terms related to a subcriterion that is based on thedifferences of the HF signal value and a reference HF signal valuecorresponding to the bit cluster of each single primary neighboring bit,said evaluation being done for all possible bit units obtained for allpossible values of said primary neighboring bits, and wherein the bitunit with the lowest value of said predetermined evaluation criterion isselected.
 5. The method as claimed in claim 4, wherein said subcriterionrelates to the squared value of the difference of the HF signal valueand a reference HF signal value corresponding to the bit cluster of eachsingle primary neighboring bit.
 6. The method as claimed in claim 4,wherein said subcriterion relates to the absolute value of thedifference of the HF signal value and a reference HF signal valuecorresponding to the bit cluster of each single primary neighboring bit.7. The method as claimed in claim 1, wherein the preliminary bitdecisions on the primary neighboring bits are obtained by use ofsoft-decision information.
 8. The method as claimed in claim 1, whereinfurther preliminary bit decisions on secondary neighboring bits, beingthe neighboring bits of said primary neighboring bits but not being partof the central bit row of said cluster, are used for determining thepreliminary bit decisions on said primary neighboring bits.
 9. Themethod as claimed in claim 8, wherein said branch metrics are calculatedas an expectation value, in particular the average taken over allpossible bit values of said secondary neighboring bits usingsoft-decision information available for said secondary neighboring bits.10. The method as claimed in claim 1, wherein said branch metrics aredetermined as the absolute value of the difference between the receivedHF signal value for the central bit of said cluster and a reference HFsignal value depending on the bit values of all bits of said cluster.11. The method as claimed in claim 1, wherein N is 2 and wherein the bitvalues of bits of a channel data stream are stored on a record carrieralong a two-dimensional channel strip of at least two bit rowsone-dimensionally evolving along a first direction and aligned with eachother along a second direction, said two directions constituting atwo-dimensional lattice of bit positions.
 12. The method as claimed inclaim 11, wherein the 2D lattice of bits is a square configuration. 13.The method as claimed in claim 11, wherein the 2D lattice of bits is ahexagonal configuration.
 14. The method as claimed in claim 13, whereinsaid channel strip comprises at least three bit rows and wherein saidhexagonal configured 2D lattice of bits comprises seven bits, threebeing located in the central bit row and two being located in an upperand lower primary neighboring bit row, respectively.
 15. The method asclaimed in claim 13, wherein preliminary bit decisions on secondaryneighboring bits are used for determining the preliminary bit decisionson said two neighboring primary bits in each primary neighboring bitrow.
 16. The method as claimed in claim 15, wherein the two primaryneighboring bits of the hexagonal cluster located in the upper and lowerprimary neighboring bit row, respectively, are grouped as primaryneighboring bit unit each bit unit being surrounded by eight neighboringbits, five of which being secondary neighboring bits and three of whichbeing the central-row bits of said hexagonal cluster, said three bitsbeing set by the bits of the two states constituting each of thebranches to be considered in the Viterbi trellis of the one-dimensionalrow-based Viterbi bit detector.
 17. The method as claimed in claim 15,wherein the two primary neighboring bits of the hexagonal clusterlocated in the upper and lower primary neighboring bit row,respectively, are grouped as a primary neighboring bit unit togetherwith one bit of the next neighboring bit row constituting a bit unitconsisting of 3 bits, each bit unit being surrounded by nine neighboringbits, six of which being secondary neighboring bits, and three of whichbeing the central-row bits of said hexagonal cluster, said three bitsbeing set by the bits of the two states constituting each of thebranches to be considered in the Viterbi trellis of the one-dimensionalrow-based Viterbi bit detector.
 18. The method as claimed in claim 16,wherein the bit values of the secondary neighboring bits being theneighboring bits of the primary neighboring bits not belonging to thecentral row of said hexagonal cluster are determined by thresholddetection using a slicer level.
 19. The method as claimed in claim 1,wherein said branch metrics are determined as the squared differencebetween the received HF signal value for the central bit of said clusterand a reference HF signal value depending on the bit values of all bitsof said cluster.
 20. The method as claimed in claim 1, wherein N is 3yielding a three-dimensional lattice of bits.
 21. The method as claimedin claim 1, wherein said row-based one-dimensional Viterbi bit detectionmethod is applied iteratively and wherein preliminary bit decisions onthe primary neighboring bits are obtained from the output of saidrow-based one-dimensional Viterbi bit detection methods in a previousiteration.
 22. A Viterbi bit detector for detecting the bit values ofbits of a channel data stream stored on a record carrier along anN-dimensional channel tube, N being at least two, of at least two bitrows one-dimensionally evolving along a first direction and beingaligned with each other along at least a second of N−1 other directions,said first direction together with said N−1 other directionsconstituting an N-dimensional lattice of bit positions, said Viterbi bitdetector comprising a Viterbi bit detection unit for application of arow-based one-dimensional Viterbi bit detection method independent foreach of the bit rows of said channel tube, said Viterbi bit detectionunit comprising: means for calculating branch metrics for all possiblestate transitions in a Viterbi trellis of a one-dimensional row-basedViterbi detector, said transitions representing a number of subsequentbits in said bit row, said bits being the central-row bits of a clusterof the N-dimensional lattice of bits, said calculating being based onthe difference of the received HF signal value with respect to areference level, wherein said reference level depends on all bits ofsaid cluster, said cluster comprising, in addition to the central-rowbits, a number of primary neighboring bits in each of a number ofneighboring bit rows on each side along said N−1 other directions ofsaid central bit row along which the one-dimensional Viterbi bitdetector is applied, and wherein preliminary bit decisions for theprimary neighboring bits in the neighboring bit rows are used fordetermining the reference level to be used for calculating said branchmetrics; and means for selecting the bit value for the central bit ofsaid cluster of the N-dimensional lattice of bits, corresponding withsaid received HF signal value, based on the calculated branch metrics.23. The bit detector as claimed in claim 22, wherein said selectingmeans comprises add-compare-select units and back-tracking units.
 24. Amethod of reproducing a user data stream, said user data stream beingerror correction code and modulation code encoded into a channel datastream and stored on a record carrier, said reproducing methodcomprising a Viterbi bit detection method for detecting the bit valuesof bits of the channel data stream stored on the record carrier along anN-dimensional channel tube, N being at least two, of at least two bitrows one-dimensionally evolving along a first direction and beingaligned with each other along at least a second of N−1 other directions,said first direction together with said N−1 other directionsconstituting an N-dimensional lattice of bit positions, a modulationcode decoding method and an error correction code decoding method,wherein said Viterbi bit detection method comprises the steps of:applying a row-based one-dimensional Viterbi bit detection methodindependent for each of the bit rows of said channel tube; calculatingbranch metrics for all possible state transitions in a Viterbi trellisof a one-dimensional row-based Viterbi detector, said transitionsrepresenting a number of subsequent bits in said bit row, said bitsbeing the central-row bits of a cluster of the N-dimensional lattice ofbits, said calculating being based on the difference of the received HFsignal value with respect to a reference level, wherein said referencelevel depends on all bits of said cluster, said cluster comprising, inaddition to the central-row bits, a number of primary neighboring bitsin each of a number of neighboring bit rows on each side along said N−1other directions of said central bit row along which the one-dimensionalViterbi bit detection method is applied, and wherein preliminary bitdecisions for the primary neighboring bits in the neighboring bit rowsare used for determining the reference level to be used for calculatingsaid branch metrics; and selecting the bit value for the central bit ofsaid cluster of the N-dimensional lattice of bits, corresponding withsaid received HF signal value, based on the calculated branch metrics.25. A reproduction device for reproduction of a user data stream, saiduser data stream being error correction code and modulation code encodedinto a channel data stream and stored on a record carrier, saidreproduction device comprising a Viterbi bit detector for detecting thebit values of bits of the channel data stream stored on the recordcarrier along an N-dimensional channel tube, N being at least two, of atleast two bit rows one-dimensionally evolving along a first directionand being aligned with each other along at least a second of N−1 otherdirections, said first direction together with said N−1 other directionsconstituting an N-dimensional lattice of bit positions, a modulationcode decoder and an error correction code decoder, wherein said Viterbibit detection unit comprising: means for calculating branch metrics forall possible state transitions in a Viterbi trellis of a one-dimensionalrow-based Viterbi detector, said transitions representing a number ofsubsequent bits in said bit row, said bits being the central-row bits ofa cluster of the N-dimensional lattice of bits, said calculating beingbased on the difference of the received HF signal value with respect toa reference level, wherein said reference level depends on all bits ofsaid cluster, said cluster comprising, in addition to the central-rowbits, a number of primary neighboring bits in each of a number ofneighboring bit rows on each side along said N−1 other directions ofsaid central bit row along which the one-dimensional Viterbi bitdetector is applied, and wherein preliminary bit decisions for theprimary neighboring bits in the neighboring bit rows are used fordetermining the reference level to be used for calculating said branchmetrics; and means for selecting the bit value for the central bit ofsaid cluster of the N-dimensional lattice of bits, corresponding withsaid received HF signal value, based on the calculated branch metrics.26. An optical recorder comprising a Viterbi bit detector for detectingthe bit values of bits of a channel data stream stored on a recordcarrier along an N-dimensional channel tube, N being at least two, of atleast two bit rows one-dimensionally evolving along a first directionand being aligned with each other along at least a second of N−1 otherdirections, said first direction together with said N−1 other directionsconstituting an N-dimensional lattice of bit positions, said Viterbidetector comprising a Viterbi bit detection unit for application of arow-based one-dimensional Viterbi bit detection method independent foreach of the bit rows of said channel tube, said Viterbi bit detectionunit comprising: means for calculating branch metrics for all possiblestate transitions in a Viterbi trellis of a one-dimensional row-basedViterbi detector, said transitions representing a number of subsequentbits in said bit row, said bits being the central-row bits of a clusterof the N-dimensional lattice of bits, said calculating being based onthe difference of the received HF signal value with respect to areference level, wherein said reference level depends on all bits ofsaid cluster, said cluster comprising, in addition to the central-rowbits, a number of primary neighboring bits in each of a number ofneighboring bit rows on each side along said N−1 other directions ofsaid central bit row along which the one-dimensional Viterbi bitdetector is applied, and wherein preliminary bit decisions for theprimary neighboring bits in the neighboring bit rows are used fordetermining the reference level to be used for calculating said branchmetrics; and means for selecting the bit value for the central bit ofsaid cluster of the N-dimensional lattice of bits, corresponding withsaid received HF signal value, based on the calculated branch metrics.